The present invention is directed to testing digital logic circuits and systems such as is found in data processing apparatus. The invention relates to scan apparatus that produces sequences of test patterns that are shifted ("scanned") into and out of the system under test, producing result signatures from which can be determined whether or not the system under test will function without fault. In particular, the invention provides apparatus and methods for functionally scan testing a memory system containing dynamic random access memory (DRAM) that may be included in the system under test.
Digital or logic systems have often been tested by applying a variety of test signals to the system, and monitoring the output signals produced in response. Adding to this technique, logic systems have also been designed to incorporate elemental memory stages (i.e., single-bit storage such as flip-flops, latches, and the like) that can be selected to function in one of two modes: A first mode in which they operate as primarily designed (a component in the logic system that operates to receive, store, and pass on system information bits in response to normal logic system control signals): and a second mode in which a number of the elemental memory stages are connected in series to form one or more extended shift registers or, as more commonly referred to in the art, "scan strings." During this second mode, bit patterns, which are typically pseudo-random in nature, are shifted or "scanned" into the scan strings so configured to place the logic system in a pseudo-random state. The logic system is returned to its first mode configuration and permitted to operate for one clock. The logic system is then returned to the second mode and the results extracted from the logic system (again by scanning) and analyzed to determine the operability of the stages and interconnections of the logic system. This testing technique is usually referred to as "scan testing."
Among the underlying principles of scan testing is that the test must be repeatable in the sense that each time a logic system is tested, the same result will be achieved if the system under test is without fault. For this reason, one limitation of scan testing has been the inability to test dynamic random access memories (DRAMs). Such memories require periodic refresh to maintain the information stored. Memory operations, such as read or write accesses, to the memory often are blocked during such refresh intervals. Typically, the intervals are asynchronous in the sense that each time a scan test is initiated, occurrence of the refresh intervals during one test may be different from that of another test. Further, it may be that the length of time of the refresh interval itself is subject to change, so that two different tests will encounter two different refresh intervals. Accordingly: a scan test performed on a digital system that includes a DRAM can produce one result when one test is conducted, and another result when another test is conducted.
These different test results, arising from the asynchronous nature of DRAMs, stems from the following: Typically, when a memory operation is requested (e.g., read or write) of a DRAM during refresh, the DRAM cannot respond: the refresh interval must complete before the DRAM is able to comply with the request. Thus, if during one scan test a read operation is requested. but not honored because of refresh, one result is produced. If the same test is run again later, but this time the same read request is honored, another, different result can be produced.
It is for this reason that scan test schemes do not test DRAMs. As a result, not only is the DRAM left untested, but the circuitry necessary to support DRAM operation is also left unchecked. In short, the entire DRAM memory system is not tested by the scan testing techniques described.
It can be seen, therefore, that in scan testing of the type to which the present invention is directed, there exists a need to be able to, at least, functionally test digital systems having memory systems that include DRAMs of the type described.